14 bit ripple counter design
Notice that the CK input is applied to all the flip-flops in parallel. Therefore, as all the flip-flops receive a clock pulse at the same instant, some method must be used to prevent all the flip-flops changing state at the same time. This of course would result in the counter outputs simply toggling from all ones to all zeros, and back again with each clock pulse.
However, with JK flip-flops, when both J and K inputs are logic 1 the output toggles on each CK pulse, but when J and K are both at logic 0 no change takes place. The binary output is taken from the Q outputs of the flip-flops. Note that on FF0 the J and K inputs are permanently wired to logic 1, so Q 0 will change state toggle on each clock pulse. In adding a third flip flop to the counter however, direct connection from J and K to the previous Q 1 output would not give the correct count.
Because Q 1 is high at a count of 2 10 this would mean that FF2 would toggle on clock pulse three, as J2 and K2 would be high. Therefore clock pulse 3 would give a binary count of 2 or 7 10 instead of 4 To prevent this problem an AND gate is used, as shown in Fig. Only when the outputs are in this state will the next clock pulse toggle Q 2 to logic 1. The outputs Q 0 and Q 1 will of course return to logic 0 on this pulse, so giving a count of 2 or 4 10 with Q 0 being the least significant bit.
Q 3 therefore will not toggle to its high state until the eighth clock pulse, and will remain high until the sixteenth clock pulse. After this pulse, all the Q outputs will return to zero. Note that for this basic form of the synchronous counter to work, the PR and CLR inputs must also be all at logic 1, their inactive state as shown in Fig.
Converting the synchronous up counter to count down is simply a matter of reversing the count. If all of the ones and zeros in the 0 to 15 10 sequence shown in Table 5. As every Q output on the JK flip-flops has its complement on Q , all that is needed to convert the up counter in Fig. Each group of gates between successive flip-flops is in fact a modified data select circuit described in Combinational Logic Module 4. This is necessary to provide the correct logic state for the next data selector.
If the control input is at logic 1 then the CK pulse to the next flip-flop is fed from the Q output, making the counter an UP counter, but if the control input is 0 then CK pulses are fed from Q and the counter is a DOWN counter. When Q 1 and Q 3 are both at logic 1, the output terminal of the limit detection NAND gate LD1 will become logic 0 and reset all the flip-flop outputs to logic 0.
Because the first time Q 1 and Q 3 are both at logic 1 during a 0 to 15 10 count is at a count of ten 2 , this will cause the counter to count from 0 to 9 10 and then reset to 0, omitting 10 10 to 15 The circuit is therefore a BCD counter, an extremely useful device for driving numeric displays via a BCD to 7-segment decoder etc.
However by re-designing the gating system to produce logic 0 at the CLR inputs for a different maximum value, any count other than 0 to 15 can be achieved. If you already have a simulator such as Logisim installed on your computer, why not try designing an Octal up counter for example. Although synchronous counters can be, and are built from individual JK flip-flops, in many circuits they will be ether built into dedicated counter ICs, or into other large scale integrated circuits LSICs.
For many applications the counters contained within ICs have extra inputs and outputs added to increase the counters versatility. The differences between many commercial counter ICs are basically the different input and output facilities offered.
Some of which are described below. Notice that many of these inputs are active low; this derives from the fact that in earlier TTL devices any unconnected input would float up to logic 1 and hence become inactive.
However leaving inputs un-connected is not good practice, especially CMOS inputs, which float between logic states, and could easily be activated to either valid logic state by random noise in the circuit, therefore ANY unused input should be permanently connected to its inactive logic state.
Count Enable CTEN for example, is a feature on counter integrated circuits, and in the synchronous counter illustrated in Fig 5. When it is set to logic 1, it will prevent the count from progressing, even in the presence of clock pulses, but the count will continue normally when CTEN is at logic 0. A common way of disabling the counter, whilst retaining any current data on the Q outputs, is to inhibit the toggle action of the JK flip-flops whilst CTEN is inactive logic 1 , by making the JK inputs of all the flip-flops logic 0.
When the count is disabled, CTEN and therefore one of the inputs on each of , E1, E2 and E3 will be at logic 0, which will cause these enable gate outputs, and the flip-flop JK inputs to also be at logic 0, whatever logic states are present on the Q outputs, and also at the other enable gate inputs. Therefore whenever CTEN is at logic 1 the count is disabled.
In this condition, when the next clock pulse is received at the CK input the flip-flops will toggle, following their normal sequence. Using a separate DATA input for each flip-flop, and a small amount of extra logic, a logic 0 on the PL will load the counter with any pre-determined binary value before the start of, or during the count.
A method of achieving asynchronous parallel loading on a synchronous counter is shown in Fig. The binary value to be loaded into the counter is applied to inputs D 0 to D 3 and a logic 0 pulse is applied to the PL input.
This logic 0 is inverted and applied to one input of each of the eight NAND gates to enable them. If the value to be loaded into a particular flip-flop is logic 1, this makes the inputs of the right hand NAND gate 1,1 and due to the inverter between the pair of NAND gates for that particular input, the left hand NAND gate inputs will be 1,0.
The result of this is that logic 0 is applied to the flip-flop PR input and logic 1 is applied to the CLR input. This combination sets the Q output to logic 1, the same value that was applied to the D input. Similarly if a D input is at logic 0 the output of the left hand NAND gate of the pair will be Logic 0 and the right hand gate output will be logic 1, which will clear the Q output of the flip-flop.
Because the PL input is common to each pair of load NAND gates, all four flip-flops are loaded simultaneously with the value, either 1 or 0 present at its particular D input. Modifications such as those described in this module make the basic synchronous counter much more versatile.
You can continue to add additional flip-flops, always inverting the output to its own input, and using the output from the previous flip-flop as the clock signal. The result is called a ripple counter, which can count to 2 n - 1 where n is the number of bits flip-flop stages in the counter. Ripple counters suffer from unstable outputs as the overflows "ripple" from stage to stage, but they do find frequent application as dividers for clock signals, where the instantaneous count is unimportant, but the division ratio overall is to clarify this, a 1-bit counter is exactly equivalent to a divide by two circuit; the output frequency is exactly half that of the input when fed with a regular train of clock pulses.
The use of flip-flop outputs as clocks leads to timing skew between the count data bits, making this ripple technique incompatible with normal synchronous circuit design styles.
In synchronous counters, the clock inputs of all the flip-flops are connected together and are triggered by the input pulses. Thus, all the flip-flops change state simultaneously in parallel. The circuit below is a 4-bit synchronous counter.
A simple way of implementing the logic for each bit of an ascending counter which is what is depicted in the adjacent image is for each bit to toggle when all of the less significant bits are at a logic high state. For example, bit 1 toggles when bit 0 is logic high; bit 2 toggles when both bit 1 and bit 0 are logic high; bit 3 toggles when bit 2, bit 1 and bit 0 are all high; and so on.
Synchronous counters can also be implemented with hardware finite-state machines , which are more complex but allow for smoother, more stable transitions. A decade counter is one that counts in decimal digits, rather than binary. A decade counter may have each that is, it may count in binary-coded decimal , as the integrated circuit did or other binary encodings. An ordinary four-stage counter can be easily modified to a decade counter by adding a NAND gate as in the schematic to the right.
It counts from 0 to 9 and then resets to zero. The counter output can be set to zero by pulsing the reset line low. The count then increments on each clock pulse until it reaches decimal 9. When it increments to decimal 10 both inputs of the NAND gate go high.
The result is that the NAND output goes low, and resets the counter to zero. A ring counter is a circular shift register which is initiated such that only one of its flip-flops is the state one while others are in their zero states. A ring counter is a shift register a cascade connection of flip-flops with the output of the last one connected to the input of the first, that is, in a ring.
Typically, a pattern consisting of a single bit is circulated so the state repeats every n clock cycles if n flip-flops are used. These counters find specialist applications, including those similar to the decade counter, digital-to-analog conversion, etc. They can be implemented easily using D- or JK-type flip-flops. In computability theory , a counter is considered a type of memory. A counter stores a single natural number initially zero and can be arbitrarily long. A counter is usually considered in conjunction with a finite-state machine FSM , which can perform the following operations on the counter:.
The following machines are listed in order of power, with each one being strictly more powerful than the one below it:. For the first and last, it doesn't matter whether the FSM is a deterministic finite automaton or a nondeterministic finite automaton. They have the same power. The first two and the last one are levels of the Chomsky hierarchy. The first machine, an FSM plus two counters, is equivalent in power to a Turing machine.
See the article on counter machines for a proof. A web counter or hit counter is a computer software program that indicates the number of visitors, or hits, a particular webpage has received. Once set up, these counters will be incremented by one every time the web page is accessed in a web browser. The number is usually displayed as an inline digital image or in plain text or on a physical counter such as a mechanical counter.
Images may be presented in a variety of fonts , or styles; the classic example is the wheels of an odometer.